US 7,608,931 B1Granted

Interconnect array formed at least in part with repeated application of an interconnect pattern

AssigneeXilinx, Inc.

InventorBrian Von Herzen

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Abstract

An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations are disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region has one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern offset from one another responsive to the offset region.

Claims11

Dependent claims

An interconnect array, comprising:

an interconnect pattern, the interconnect pattern having at least ten interconnect locations, one of the at least ten interconnect locations being for a power interconnect, another one of the at least ten interconnect locations being for a ground interconnect, and at least eight remaining interconnect locations of the at least ten interconnect locations being for additional interconnects to provide at least eight additional interconnects that are for signals and are not for power or ground, one of either the power interconnect or the ground interconnect being located in a medial region of the interconnect pattern;
a first two of the at least eight additional interconnect locations located horizontally adjacent to the medial region, one of the first two being located on a right side of the medial region, another one of the first two being located on a left side of the medial region;
a second two of the at least eight additional interconnect locations located vertically adjacent to the medial region, one of the second two being located on a top side of the medial region, another one of the second two being located on a bottom side of the medial region;
an offset region of the at least ten interconnect locations located either horizontally or vertically adjacent to one of either the first two or the second two of the at least eight additional interconnect locations, the offset region being external to a perimeter defined by the at least eight additional interconnect locations;
and
the one of either the power interconnect or the ground interconnect that is not located in the medial region being located in the offset region.

3 more elements

An interconnect array, comprising:

a first interconnect pattern, the first interconnect pattern having ten first interconnect locations, one of the first interconnect locations being for a power interconnect, another one of the first interconnect locations being for a ground interconnect, and eight of the ten first interconnect locations remaining being for additional interconnects that are for signals and are not for power or ground, one of either the power interconnect or the ground interconnect being located in a medial region of the first interconnect pattern;
a first two of the eight of the ten first interconnect locations located diagonally adjacent to and above the medial region;
a second two of the eight of the ten first interconnect locations located diagonally adjacent to and below the medial region;
an offset region of the ten first interconnect locations located either horizontally or vertically adjacent to one of either the first two or the second two of the eight of the ten first interconnect locations, the offset region being external to a perimeter defined by the eight of the ten first interconnect locations;
and
the one of either the power interconnect or the ground interconnect that is not located in the medial region being located in the offset region.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/364,262Filed 2 Feb 2009 · division
Priority: 5 May 2005
Granted: 27 Oct 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10W 72/00
Interconnections or connectors in packages
H10W 90/724
Of bump connectors: between a chip and a stacked insulating package substrate, interposer or RDL
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Family

Application11/123,526Parent of this division · filed 5 May 2005
US 7,501,341 B1Parent of this division
US 7,608,931 B1This patent

From the US filing history. Foreign family members aren’t listed.

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