Robust deep trench isolation

An electronic device comprising:

• a semiconductor body having a substrate layer and a further layer extending from the substrate layer to a first surface spaced apart from the substrate layer;
• a dielectric lined isolation trench in the semiconductor body extending from the first surface toward the substrate layer and dividing the further layer into at least two regions, a first region on a first side of the dielectric lined isolation trench and a second region on a second side of the dielectric lined isolation trench;
• wherein at least one of the first and second regions has first, second, third and fourth portions abutting one of the first or second sides of the dielectric lined isolation trench;
• and
• wherein the first portion of a first conductivity type and first dopant concentration C1 overlies the substrate layer, the second portion of a second, opposite conductivity type and second dopant concentration C2 overlies at least part of the first portion, the third portion of the second conductivity type and a third dopant concentration C3 overlies the second portion, and the fourth portion of the second conductivity type and a fourth dopant concentration C4 overlies the third portion;
• and wherein C1<C2<C3>C4.

A semiconductor device, comprising:

• a semiconductor body having a substrate layer and a further layer extending from the substrate layer to a first surface of the semiconductor body;
• a dielectric lined isolation trench extending into the semiconductor body from the first surface so that at least one dielectric lined sidewall is in contact with stacked portions of the further layer;
• and
• wherein a first portion of the further layer has a first dopant concentration C1, a second overlying portion of the further layer has a second dopant concentration C2, and a third overlying portion of the further layer has a third dopant concentration C3, such that C1<C2<C3 and that C1 and C2 are of opposite conductivity type and C2 and C3 are of the same conductivity type.