Non-volatile semiconductor memory device and method for manufacturing the same

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• a memory cell section provided with a plurality of memory cell transistors each having a first gate electrode on the semiconductor substrate, a first insulating film formed at a side wall of the first gate electrode as well as at the lower periphery to the side wall, a first electric charge accumulation layer made of an insulating film formed on top of the first insulating film lower periphery and at the side of the first insulating film, and a first sidewall made of an insulating film formed at a side of the first electric charge accumulation layer;
• and
• a periphery circuitry section which is formed in the vicinity of the memory cell section and provided with a plurality of periphery circuitry transistors each having a second gate electrode, a second insulating film formed on a side wall of the second gate electrode and at the lower periphery to the side wall, a second electric charge accumulation layer made of an insulating layer formed on top of the second insulating film lower periphery and at the side of the second insulating film, and a second sidewall made of an insulating film formed at a side of the second insulating film, wherein a film thickness of the lower periphery in the second insulating film differs from that of the lower periphery in the first insulating film;
• the periphery circuitry section controlling memory operations with respect to the memory cell section.

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• a memory cell section provided with a plurality of memory cell transistors each having a first gate electrode on the semiconductor substrate, a first insulating film formed at a side wall of the first gate electrode as well as at the lower periphery to the side wall, a first electric charge accumulation layer made of an insulating film formed on top of the first insulating film lower periphery and at a side of the first insulating film, a first sidewall made of an insulating film formed at a side of the first electric charge accumulation layer, a first low concentration impurity layer formed under the lower periphery of the first insulating layer, and a first high concentration impurity layer formed at the outer border of the first low concentration impurity layer;
• and
• a periphery circuitry section formed in the vicinity of the memory cell section and provided with a plurality of periphery circuitry transistors each having a second gate electrode, a second insulating film formed on a side wall of the second gate electrode and at the lower periphery to the side wall, a second electric charge accumulation layer made of an insulating layer formed on top of the second insulating film lower periphery and at a side of the second insulating film, a second sidewall made of an insulating film formed at a side of the second insulating film, a second low concentration impurity layer formed under the lower periphery of the second insulating film and having a different width in the substrate surface direction from that of the first low concentration impurity layer, and a second high concentration impurity layer formed at the outer border of the second low concentration impurity layer;
• the periphery circuitry section controlling memory operations with respect to the memory cell section.

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• a memory cell section provided with a plurality of memory cell transistors each having a first gate electrode on the semiconductor substrate, a first insulating film formed at a side wall of the first gate electrode as well as at the lower periphery to the side wall, a first electric charge accumulation layer made of an insulating film formed on the top of the first insulating film lower periphery and at a side of the first insulating film, a first sidewall made of an insulating film formed at a side of the first electric charge accumulation layer, and a first semiconductor impurity layer positioned under the lower periphery of the first insulating film and outside the lower periphery, and formed separated from the first gate electrode by a first distance;
• and
• a periphery circuitry section formed in the vicinity of the memory cell section and provided with a plurality of periphery circuitry transistors each having a second gate electrode, a second insulating film formed at a side wall of the second gate electrode as well as at the lower periphery to the side wall, a second electric charge accumulation layer made of an insulating layer formed on the top of the second insulating film lower periphery and at a side of the second insulating film, a second sidewall made of the insulating film formed at a side of the second insulating film, and a second semiconductor impurity layer positioned under the lower periphery of the second insulating film and outside the lower periphery, and formed separated from the second gate electrode by a second distance different from that of the first distance.