High electron mobility transistor with mesa structure and reduced gate leakage current

A semiconductor device, comprising:

• a semiinsulating substrate;
• a layered structure of compound semiconductor, which is provided on said semiinsulating substrated as a mesa structure having a pyramid shape with a rectangular base, and contains an active channel layer and a donor layer, which forms a hetero-junction with said active channel layer, as intermediate layers;
• first and second metal main electrodes, which are provided on an upper surface of said mesa structure being away from each other in a channel length direction and extending down along respective sides of said mesa structure so as to have inclined portions relative to said substrate;
• a metal control electrode provided between the first metal main electrode and the second metal main electrode;
• and
• first and second ion implantation regions, which are provided at edge sections of said mesa structure between said first and second main metal electrodes, facing each other in a channel width direction, and extending from an upper surface of said mesa structure to a depth level below said active channel layer, said first ion implantation region and said second ion implantation region being situated under the metal control electrode and away from the first metal main electrode and the second metal main electrode,
• wherein said first and second ion implantation regions isolate said active channel layer from said metal control electrode so as to prevent said metal control electrode from contacting said active channel layer.

A. semiconductor device, comprising:

• an InP substrate;
• a layered structure of compound semiconductor, which is formed as a mesa structure, and contains InAlAs buffer layer, InGaAs active channel layer provided on said InAlAs buffer layer, InAlAs donor layer formed on said InGaAs active channel layer, and an n+-InGaAs capping layer formed on said InAlAs donor layer;
• first and second metal main electrodes, which are provided on said layered structure, being away from each other on an upper surface of said n+-InGaAs capping layer;
• a metal control electrode provided on the InAlAs donor layer between the first metal main electrode and the second metal main electrode, said metal control electrode penetrating the n+-InGaAs capping layer without contact;
• first and second ion implantation regions, which are provided at edge sections of said mesa structure between said first and second metal main electrodes, facing each other ion a channel width direction, extending from an upper surface of said capping layer to a depth level below said InGaAs active channel layer, and disposed at only sides of said InGaAs active channel layer that do not constitute ends thereof;
• and
• an interlayer spacer film provided on an upper side of said mesa structure including said first and second metal main electrodes,
• wherein said metal control electrode extends along said channel width direction to inside of said first and second ion implantation regions, and also extends on said interlayer spacer film to outside of said mesa structure.