Transistor forming methods

A transistor forming method comprising:

• forming an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate;
• removing some of semiconductor material of the island and forming a trench defining a fin of semiconductor material in the island, the fin have a top, opposing sidewalls, and opposing endwalls and a portion of the island remaining at a bottom of the trench;
• after forming the trench, forming a dielectric spacer in the trench over the bottom, the opposing sidewalls, and the opposing endwalls and laterally surrounding the fin, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness;
• forming a gate line on and in contact with the semiconductor material exposed above the spacer, the gate line extending over the opposing sidewalls and over the top of the fin;
• forming an interlayer dielectric over areas of the fin intended for source/drain regions;
• forming contact openings through the interlayer dielectric and exposing the areas intended for source/drain regions and at least a portion of the spacer proximate the areas;
• in operational association with the gate line, forming the source/drain regions in the fin;
• forming a source/drain plug in contact with the exposed portion of the spacer and in electrical connection with the top, one of the opposing endwalls, and both of the opposing sidewalls of the fin of one of the source/drain regions;
• and
• forming another source/drain plug in contact with the exposed portion of the spacer and in electrical connection with at least the top and both of the opposing sidewalls of the fin of another of the source/drain regions.

A transistor forming method comprising:

• forming an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate;
• removing some of semiconductor material of the island and forming a trench defining a fin of semiconductor material in the island, the fin have a top, opposing sidewalls, and opposing endwalls and a portion of the island remaining at a bottom of the trench;
• after forming the trench, forming a dielectric spacer in the trench over the bottom, the opposing sidewalls, and the opposing endwalls and laterally surrounding the fin, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness;
• forming line openings through the spacer and exposing through the line openings some of the semiconductor material of the island at the bottom of the trench and some of the semiconductor material of the opposing sidewalls of the fin;
• forming a gate line on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin;
• forming gate line insulation on opposing sidewalls of the gate line;
• forming an interlayer dielectric over areas of the fin intended for source/drain regions;
• forming contact openings through the interlayer dielectric and exposing the areas intended for source/drain regions and at least a portion of the spacer proximate the areas;
• in operational association with the gate line, forming the source/drain regions in the fin through the contact openings;
• forming a source/drain plug in contact with the exposed portion of the spacer and in electrical connection with the top, one of the opposing endwalls, and both of the opposing sidewalls of the fin of an exposed source/drain region, the spacer thickness constituting a height offset between the source/drain plug and the semiconductor material of the island at the bottom of the trench;
• and
• forming another source/drain plug in contact with the exposed portion of the spacer and in electrical connection with at least the top and both of the opposing sidewalls of the fin of another exposed source/drain region, the spacer thickness constituting a height offset between the other source/drain plug and the semiconductor material of the island at the bottom of the trench.