Programmable resistive RAM and manufacturing method

A method of forming an integrated circuit with nonvolatile memory cells, comprising:

• forming conductive rows accessing the nonvolatile memory cells by row;
• forming dielectric layers above said conductive rows, including:
• forming a first dielectric layer above said conductive rows;
• and
• forming a second dielectric layer at least partly above the first dielectric layer, wherein the first and second dielectric layers have an etching selectivity difference;
• forming interlayer contacts through the dielectric layers to conductively connect with the conductive rows;
• reducing a cross-section of a part of the interlayer contacts in a self-aligned process, including:
• forming a third dielectric layer at least partly covering the interlayer contacts;
• removing only part of the third dielectric layer covering the interlayer contacts to leave dielectric structures at least partly covering the interlayer contacts, including wet etching said part of the third dielectric layer;
• and
• reducing a cross-section of a part of the interlayer contacts by removing material from a part of the interlayer contacts uncovered by the dielectric structures;
• forming programmable resistive elements of the nonvolatile memory cells to conductively connect with the interlayer contacts;
• and
• forming conductive columns accessing the nonvolatile memory cells by column to conductively connect with the programmable resistive elements.

An integrated circuit with nonvolatile memory cells, comprising:

• conductive rows accessing the nonvolatile memory cells by row;
• a first dielectric layer above said conductive rows;
• a second dielectric layer above said first dielectric layer, the second dielectric having a different etch rate from the first dielectric layer;
• programmable resistive elements of the nonvolatile memory cells above the second dielectric layer;
• interlayer contacts through the dielectric layers to conductively connect with the conductive rows, each including:
• a first part adjacent to and conductively connected to at least one of the programmable resistive elements, the first part having a first cross-section, the first part having a top surface, wherein the top surface is higher than the second dielectric layer;
• and
• a second part adjacent to and conductively connected to the first part, the second part conductively connected to the conductive rows, the second part having a second cross-section larger than the first cross-section, the second cross-section being substantially uniform between the first part and the conductive rows;
• and
• conductive columns accessing the nonvolatile memory cells by column to conductively connect with the programmable resistive elements.