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US 7,465,970 B2Granted
Common pass gate layout of a D flip flop
AssigneeFaraday Technology Corp.
InventorsJeng-Huang Wu, Chiung-Yu Feng, Chien-Chih Huang, Yu-Wen Tsai
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Abstract
A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
Claims9
A common pass gate layout of a D flip-flop comprising:
- a first n diffusion region;
- a second n diffusion region;
- a first poly-silicon conductor extending from the first n diffusion region to the second n diffusion region, for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively;
- a second poly-silicon conductor extending from the first n diffusion region to the second n diffusion region, for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively;
- a first p diffusion region adjacent to the second n diffusion region;
- a second p diffusion region;
- a third poly-silicon conductor extending from the first p diffusion region to the second p diffusion region, for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively;
- a fourth poly-silicon conductor extending from the first p diffusion region to the second p diffusion region, for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively;
- a first clock output pin coupled to the first poly-silicon conductor and the fourth poly-silicon conductor, for outputting a first clock signal;
- and
- a second clock output pin coupled to the second poly-silicon conductor and the third poly-silicon conductor, for outputting a second clock signal.
8 more elements
A common pass gate layout of a D flip-flop comprising:
- a first semiconductor cell comprising:
- a first n diffusion region;
- a second n diffusion region;
- a first poly-silicon conductor extending from the first n diffusion region to the second n diffusion region, for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively;
- a second poly-silicon conductor extending from the first n diffusion region to the second n diffusion region, for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively;
- a first p diffusion region adjacent to the second n diffusion region;
- a second p diffusion region;
- a third poly-silicon conductor extending from the first p diffusion region to the second p diffusion region, for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively;
- and
- a fourth poly-silicon conductor extending from the first p diffusion region to the second p diffusion region, for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively;
- a second semiconductor cell comprising:
- a first clock output pin for outputting a first clock signal;
- and
- a second clock output pin for outputting a second clock signal;
- a fifth poly-silicon conductor extending from the first clock output pin to the first poly-silicon conductor and the fourth poly-silicon conductor;
- and
- a sixth poly-silicon conductor extending from the second clock output pin to the second poly-silicon conductor and the third poly-silicon conductor.
14 more elements
Dependencies are inferred from the claim text.