Method for fabricating an SOI device

A method for fabricating a silicon on insulator (SOI) integrated circuit comprising a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer, the method comprising the steps of:

• impurity doping a portion of the monocrystalline silicon layer to form a first capacitor plate;
• forming a gate insulator layer overlying the portion of the monocrystalline silicon layer;
• depositing a layer of polycrystalline silicon overlying the gate insulator layer;
• patterning the layer of polycrystalline silicon to form a second capacitor plate having a substantially rectangular shape with chamfered corners;
• ion implanting impurity determining ions into the monocrystalline silicon layer in self alignment with the second capacitor plate to form a contact to the first capacitor plate;
• forming a first voltage bus coupled to the first capacitor plate;
• and
• forming a second voltage bus coupled to the second capacitor plate.

A method for fabricating a silicon on insulator (SOI) device comprising a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer, the method comprising the steps of:

• impurity doping a portion of the monocrystalline silicon layer to form a first capacitor plate;
• forming a gate insulator layer overlying the portion of the monocrystalline silicon layer;
• depositing a layer of gate electrode material overlying the gate insulator layer;
• patterning the layer of gate electrode material to form a second capacitor plate having a substantially rectangular shape with chamfered corners;
• ion implanting impurity determining ions into silicon substrate to form a substrate contact;
• forming a first voltage bus coupled to the first capacitor plate and to the substrate contact;
• and
• forming a second voltage bus coupled to the second capacitor plate.

A method for fabricating a silicon on insulator (SOI) device comprising a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer, the method comprising the steps of:

• forming an MOS capacitor coupled between a first voltage bus and a second voltage bus, the MOS capacitor having a gate electrode material forming a first plate of the MOS capacitor and coupled to the first voltage bus and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor and coupled to the second bus;
• and
• forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate, wherein the step of forming an electrical discharge path comprises the steps of:
• forming a dielectric isolation region extending through the monocrystalline silicon layer to the buried insulator layer;
• etching an opening through the dielectric isolation region and the buried insulation layer to expose a portion of the silicon substrate;
• ion implanting conductivity determining impurities through the opening to form an electrical contact area in the substrate;
• and
• coupling the second voltage bus to the electrical contact area in the substrate.

A method for fabricating a silicon on insulator (SOI) integrated circuit comprising a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer, the method comprising the steps of:

• forming a plurality of isolation structures extending through the monocrystalline silicon layer to the buried insulator layer to form a plurality of electrically isolated regions in the monocrystalline silicon layer;
• doping a first electrically isolated region and a second electrically isolated region of the plurality of electrically isolated regions with N-type conductivity determining dopant impurities;
• doping a third electrically isolated region of the plurality of electrically isolated regions with P-type conductivity determining dopant impurities;
• etching an opening through one of the plurality of isolation structures and the buried insulator layer to expose a portion of the silicon substrate;
• forming a gate insulator layer overlying the first electrically isolated region, the second electrically isolated region and the third electrically isolated region;
• forming a first gate electrode overlying the gate insulator overlying the first electrically isolated region, a conductive capacitor electrode overlying the gate insulator overlying the second electrically isolated region, and a second gate electrode overlying the gate insulator overlying the third electrically isolated region;
• ion implanting P-type conductivity determining dopant ions to form P-type source and drain regions of a PMOS transistor self aligned with the first gate electrode in the first electrically isolated region and a P-type contact in the exposed portion of the silicon substrate;
• ion implanting N-type conductivity determining dopant ions to form N-type source and drain regions of an NMOS transistor self aligned with the second gate electrode in the third electrically isolated region and to form a second capacitor contact self aligned with the conductive capacitor electrode in the second electrically isolated region;
• and
• forming a first bus conductor coupled to the conductive capacitor electrode and to the drain of the NMOS transistor and a second bus conductor coupled to the second capacitor contact, the P-type contact in the exposed portion of the silicon substrate, and the drain of the PMOS transistor.