US 7,423,903 B2 · Single-gate non-volatile memory and operation method thereof

Abstract

A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Claims7

Dependent claims

An operation method of a single-gate non-volatile memory,

wherein said single-gate non-volatile memory comprises:
a P-type semiconductor substrate;
a transistor, disposed in said P-type semiconductor substrate, and having a first electrically-conductive gate and a plurality of first ion-doped regions, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain;
and
a capacitor structure, disposed in said P-type semiconductor substrate, and having a second electrically-conductive gate and a second ion-doped region;
wherein said first electrically-conductive gate and said second electrically-conductive gate being electrically interconnected to form a single floating gate;
wherein said operation method is characterized in:
a substrate voltage Vsub, a source voltage Vs, a drain voltage Vd, a control gate voltage Vc are respectively applied to said P-type semiconductor substrate, said source, said drain and said second ion-doped region, and said voltages meet the following conditions:
in writing said memory:
Vsub is grounded, and
Vd>Vs>0, and
Vc>Vs>0;
and
in erasing said memory:
Vsub is grounded, and
Vd>Vc>Vs≧0.

13 more elements

Dependencies are inferred from the claim text.

Single-gate non-volatile memory and operation method thereof

Life of this patent

Single-gate non-volatile memory and operation method thereof

Life of this patent

Abstract

Claims7