Radiation-hardened silicon-on-insulator CMOS device, and method of making the same
AssigneePeregrine Semiconductor Corporation
InventorsAnthony M. Miscione, George Imthurn, Eugene F. Lyons, Michael A. Stuber
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Abstract
A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.
Claims18
A silicon-on-insulator metal oxide semiconductor device comprising:
- an ultrathin silicon layer on a sapphire substrate;
- at least one P-channel MOS transistor formed in the ultrathin silicon layer;
- N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire substrate is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer.
A silicon-on-insulator metal oxide semiconductor device comprising:
- an ultrathin silicon layer on a sapphire substrate;
- at least one P-channel MOS transistor formed in the ultrathin silicon layer;
- N-type impurity implanted within the sapphire substrate such that peak N-type impurity concentration within the sapphire substrate is disposed at least 0.05 microns from a silicon-sapphire back interface.
A silicon-on-insulator metal oxide semiconductor device comprising:
- an ultrathin silicon layer on a sapphire substrate;
- at least one P-channel MOS transistor formed in the ultrathin silicon layer;
- N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration of approximately 1.0×1019 ions/cm2in the sapphire layer, which is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer and which is disposed at least 0.05 microns from a silicon-sapphire back interface.
A silicon-on-insulator metal oxide semiconductor device comprising:
- an ultrathin silicon layer on a sapphire substrate;
- at least one P-channel MOS transistor formed in the ultrathin silicon layer;
- wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;
- wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region;
- and
- wherein peak N-type dopant concentration is at least 10 times higher in the sapphire substrate than peak N-type dopant concentration in the P-channel region.
A silicon-on-insulator metal oxide semiconductor device comprising:
- an ultrathin silicon layer on a sapphire substrate;
- at least one P-channel MOS transistor formed in the ultrathin silicon layer;
- wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;
- wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region;
- and
- wherein peak N-type dopant concentration is in the sapphire substrate and is disposed at least 0.05 microns from a silicon-sapphire back interface.
Dependencies are inferred from the claim text.