Fabrication methods for memory cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorKern-Huat Ang
Life of this patent
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Abstract
A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer are patterned into a first line. A dielectric layer is formed on the substrate with an opening exposing the first line. A column comprising a second diode component, a buffer layer, and an anti-fuse layer is formed in the opening. A second line is formed connecting the column on the dielectric layer running generally perpendicularly to the first line.
Claims8
A method for fabricating a memory cell, comprising:
- forming a first conductive line and a first diode component on a substrate sequentially;
- forming a dielectric layer on the substrate covering the first conductive line and the first diode component;
- etching the dielectric layer to create an opening exposing the first diode component;
- forming a stack filling the opening, comprising a second diode component, a buffer layer and an anti-fuse layer;
- and
- forming a second conductive line on the dielectric layer, connecting the stack and generally perpendicularly to the first conductive line,
- wherein the dielectric layer is formed before the stack of the second diode component, the buffer layer and the anti-fuse layer is filled, and
- wherein the stack is formed by the steps of:
- oxidizing a surface of the first diode component to create an oxide layer to act as the anti-fuse layer;
- filling the opening with silicon to form a silicon column contacting the anti-fuse layer;
- and
- performing an ion implantation to the silicon column to form a heavily doped upper portion of the silicon column as the buffer layer and a lightly doped lower portion of the silicon column as the second diode component.
A method for fabricating a memory cell, comprising:
- forming a first conductive line in a first dielectric layer on a substrate, exposing a surface of the first conductive line;
- forming a first column comprising a first diode component on the exposed first conductive layer;
- forming a second dielectric layer covering the first dielectric layer and the first conductive line and the first diode component;
- etching the second dielectric layer to create an opening exposing the first diode component;
- forming a second column filling the opening, comprising a second diode component, a buffer layer and an anti-fuse layer;
- and
- forming a second conductive line on the second dielectric layer, connecting the second column and generally perpendicularly to the first conductive line,
- wherein the second dielectric layer is formed before the second column of the second diode component, the buffer layer and the anti-fuse layer is filled, and
- wherein the second diode component and the buffer layer are formed by the steps of:
- oxidizing a surface of the first diode component to create an oxide layer to act as the anti-fuse layer;
- filling the opening with silicon to form a silicon column contacting the anti-fuse layer;
- and
- performing an ion implantation on the silicon column to form a heavily doped upper portion of the silicon column as the buffer layer and a lightly doped lower portion of the silicon column as the second diode component.
Dependencies are inferred from the claim text.