US 7,407,871 B2 · Method for passivation of plasma etch defects in DRAM devices

Abstract

A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.

Claims18

Dependent claims

A method of forming a metal oxide semiconductor (MOS) device on a semiconductor substrate featuring passivation of defects at or near the top surface of said semiconductor substrate, comprising the steps of:

forming an insulator isolation region in a top portion of a first region of said semiconductor substrate;
forming a gate insulator layer on a second region of said semiconductor substrate, wherein said second region is not occupied by said insulator isolation region;
depositing a group of layers;
performing a plasma dry etch procedure to remove said group of layers from a first portion of said gate insulator layer while defining a gate electrode structure comprised of said group of layers on a second portion of said gate insulator layer;
performing a first ion implantation procedure to form a source/drain region in portions of said second region of said semiconductor substrate not overlaid by said gate electrode structure;
forming a first insulator spacer on a lower portion of said gate electrode structure;
performing a second ion implantation procedure placing implanted ions into a top portion of said source/drain region for passivating said defects;
forming a second insulator spacer on said gate electrode structure and on said first insulator spacer;
and
forming raised source/drain contacts on top of exposed regions of said source/drain region.

7 more elements

A method of forming a MOS device on a semiconductor substrate wherein defects located near the top surface of said semiconductor substrate are passivated via an arsenic implantation performed after completion of all high temperature furnace processing at temperatures above 890° C., comprising the steps of:

forming a silicon dioxide gate insulating layer on said semiconductor substrate;
depositing a composite layer on said silicon dioxide gate insulating layer, wherein said composite layer is comprised of an underlying polysilicon layer, a tungsten nitride layer, a tungsten layer and an overlying silicon nitride layer;
performing a plasma dry etch procedure to remove portions of said composite layer from a second portion of said silicon dioxide gate insulating layer forming a gate electrode structure on a first portion of said silicon dioxide gate insulating layer with said gate electrode structure comprised of an underlying polysilicon shape defined from unremoved portions of said polysilicon layer, a tungsten nitride shape defined from unremoved portions of said tungsten nitride layer, a tungsten shape defined from unremoved portions of said tungsten layer and an overlying silicon nitride shape defined from unremoved portions of said silicon nitride layer and with said plasma dry etching procedure creating said defects in or near the top surface of a region of said semiconductor substrate underlying said second portion of said silicon dioxide gate insulating layer;
forming a source/drain region in portions of said semiconductor substrate not covered by said gate electrode structure;
performing a thermal oxidation procedure to form a silicon oxide spacer on the sides of said polysilicon shape defined from unremoved portions of said polysilicon layer;
performing said arsenic implantation procedure through said second portion of silicon dioxide gate insulating layer and into a top portion of said source/drain region passivating said defects;
forming a silicon nitride spacer on sides of said gate electrode structure and on sides of said silicon oxide spacer;
and
forming raised source/drain silicon contacts on top of exposed regions of said source/drain region.

6 more elements

Dependencies are inferred from the claim text.

Method for passivation of plasma etch defects in DRAM devices

Life of this patent

Method for passivation of plasma etch defects in DRAM devices

Life of this patent

Abstract

Claims18