Pitch reduction integrating formation of memory array and peripheral circuitry

A process for fabricating a memory array, comprising:

• applying a first mask on a surface of a memory-array material, the first mask being patterned to define a first set of structures of the memory array and to cover an area of the surface where peripheral circuitry of the memory array is to be formed, the first set of structures from which memory-array elements are formed having a first pitch;
• etching the memory-array material to form the first set of structures, the etching not removing portions of memory-array material from which the peripheral circuitry is to be formed;
• removing the first mask to expose the area of the surface where peripheral circuitry of the memory array is to be formed;
• applying a second mask on the surface of the memory-array material, the second mask being patterned to define the memory-array elements and the peripheral circuitry, the memory-array elements having a second pitch that is less than the first pitch;
• and
• etching the memory-array material to form concurrently the memory array and peripheral circuitry.