Trench capacitor and a method for manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsMasaru Kito, Hideaki Aochi
Life of this patent
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Abstract
A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity having a first conductivity type, at least a second doped polysilicon layer filled in the upper portion through a second dielectric film and doped with a second impurity different from the first impurity, the second impurity having the first conductivity type, and a buried strap layer provided on the second doped polysilicon layer and composed of the first doped polysilicon layer.
Claims16
A method for manufacturing a trench capacitor comprising:
- forming a trench in a semiconductor substrate;
- forming a first dielectric film on an inner surface of the trench;
- filling a first doped amorphous silicon layer, doped with a first impurity, in the trench and having a first conductivity type;
- removing the first doped amorphous silicon layer and the first dielectric film to a first depth to expose an inner wall of an upper portion of the trench;
- forming a second dielectric film on the exposed inner wall of the trench;
- selectively removing the second dielectric film from the bottom of the trench to expose a surface of the first doped amorphous silicon layer;
- filling at least a second doped amorphous silicon layer, doped with a second impurity, in the trench, the second impurity, in the trench, the second impurity being different from the first impurity and having the first conductivity type;
- etching back the second doped amorphous silicon layer to a second depth to remove an exposed second dielectric film;
- and
- forming a buried strap layer on the second doped amorphous silicon layer, the buried strap layer being formed of the first doped amorphous silicon layer.
A method for manufacturing a trench capacitor comprising:
- forming a trench in a semiconductor substrate;
- forming a first dielectric film on an inner wall of the trench;
- filling a first doped amorphous silicon layer, doped with a first impurity having a first conductivity type, in the trench;
- removing the first doped amorphous silicon layer and the first dielectric film to a first depth to expose the inner wall of the trench;
- forming a second dielectric film on the exposed inner wall of the trench;
- selectively removing the second dielectric film from the trench to expose a surface of the first doped amorphous silicon layer;
- filling a second doped amorphous silicon layer, doped with the first impurity having the first conductivity type, in the trench;
- filling a third doped amorphous silicon layer, doped with a second impurity having the first conductivity type, through the second dielectric film in the trench, the second impurity being different from the first impurity and having a greater diffusion coefficient than that of the first impurity;
- etching back the third doped amorphous silicon layer to a second depth;
- selectively removing an exposed portion of the second dielectric film from the inner wall of the trench;
- and
- forming a fourth doped amorphous silicon layer over the third doped amorphous layer, the fourth doped amorphous layer having the first impurity with the first conductivity type.
Dependencies are inferred from the claim text.