System and method for providing a dry-wet-dry etch procedure to create a sidewall profile of a via
AssigneeNational Semiconductor Corporation
InventorVictor M. Torres
Life of this patent
Estimating the term…
Abstract
A system and method is disclosed for providing a dry-wet-dry etch procedure to create a sidewall profile of a via in a semiconductor device. A first vertical anisotropic dry etch process is applied to etch through a first portion of a dielectric layer. An isotropic wet etch process is then applied to etch a sloping surface in the sidewalls of the via cavity. A second vertical anisotropic dry etch process is then applied to extend the sloping sidewalls of the via cavity down to a substrate of the semiconductor device. The smooth sloping surfaces of the sidewalls are formed without a prior art concave surface of the type that interferes with a via fill process.
Claims20
A method for forming a via in a semiconductor device of a type that comprises a silicon substrate with an embedded first metal layer, said silicon substrate and said embedded first metal layer covered with a dielectric layer, and said dielectric layer covered with a resist mask having portions that form an aperture through said resist mask, said method comprising the steps of:
- applying a first vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer;
- etching a via cavity through a top portion of said dielectric layer with said first vertical anisotropic dry etch process;
- applying an isotropic wet etch process through said aperture in said resist mask to sidewalls of said via;
- and
- etching a sloping surface in said sidewalls of said cavity with said isotropic wet etch process cavity wherein said isotropic wet etch process is applied to said sidewalls of said via cavity for a period of time selected so that an amount of said dielectric layer that is removed by a lateral portion of said isotropic wet etch process allows an application of a subsequent second vertical anisotropic dry etch process to create smooth sidewalls for said via cavity.
A method for forming a via in a semiconductor device of a type that comprises a silicon substrate with an embedded first metal layer, said silicon substrate and said embedded first metal layer covered with a dielectric layer, and said dielectric layer covered with a resist mask having portions that form an aperture through said resist mask, said method comprising the steps of:
- applying a first vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer;
- etching a via cavity through a top portion of said dielectric layer with said first vertical anisotropic dry etch process;
- applying an isotropic wet etch process through said aperture in said resist mask to sidewalls of said via cavity;
- etching a sloping surface in said sidewalls of said cavity with said isotropic wet etch process;
- applying a second vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer;
- and
- etching an extension of said via cavity through a bottom portion of said dielectric layer with said second vertical anisotropic dry etch process down to said first metal layer in said silicon substrate of said semiconductor device.
A method for forming a via in a semiconductor device of a type that comprises a silicon substrate with an embedded first metal layer, said silicon substrate and said embedded first metal layer covered with a dielectric layer, and said dielectric layer covered with a resist mask having portions that form an aperture through said resist mask, said method comprising the steps of:
- applying a first vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer;
- etching a via cavity through a top portion of said dielectric layer with said first vertical anisotropic dry etch process;
- applying an isotropic wet etch process through said aperture in said resist mask to sidewalls of said via cavity for a period of time selected so that an amount of said dielectric layer that is removed by a lateral portion of said isotropic wet etch process allows an application of a subsequent second vertical anisotropic dry etch process to create smooth sidewalls for said via cavity;
- and
- etching a sloping surface in said sidewalls of said cavity with said isotropic wet etch process.
A via cavity in a semiconductor device of a type that comprises a silicon substrate with an embedded first metal layer, said silicon substrate and said embedded first metal layer covered with a dielectric layer, and said dielectric layer covered with a resist mask having portions that form an aperture through said resist mask, said via cavity formed by the steps of:
- applying a first vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer to etch said via cavity through a top portion of said dielectric layer;
- applying an isotropic wet etch process through said aperture in said resist mask to sidewalls of said via cavity to etch a sloping surface in said sidewalls of said cavity;
- and
- applying a second vertical anisotropic dry etch process through said aperture in said resist mask to said dielectric layer to etch an extension of said via cavity through a bottom portion of said dielectric layer down to said first metal layer in said silicon substrate of said semiconductor device.
Dependencies are inferred from the claim text.