Test structure for automatic dynamic negative-bias temperature instability testing

A method of generating a reduced capacitance semiconductor test structure on a substrate to provide for the automatic dynamic stress and device characterization test of semiconductor devices for Negative Bias Temperature instability said method comprising:

• creating an imbedded semiconductor device inverter with a PMOS device and a NMOS device to provide a 180 degree phase shift output from the circuit input dynamic stress test first voltage Vpulse;
• creating first and second imbedded NMOS electronic switch devices;
• creating a first PMOS test device for dynamic NBTI stress and device characterization;
• providing the circuit with a second voltage Vdd, a third voltage Vss, a fourth voltage Vd, a fifth voltage Vc, and a sixth voltage Vg;
• creating terminal access pads said first Vpulse, second Vdd, third Vss, fourth Vd, fifth Vc and sixth Vg voltage sources.