Coupling of signals between adjacent functional blocks in an integrated circuit chip

In an integrated circuit chip including a plurality of metal layers, first arid second supply potentials and at least two adjacent logic blocks, a modifiable circuit for coupling the at least two adjacent logic blocks, comprising:

• a plurality of modifiable cycles formed between the at least two adjacent logic blocks, each cycle having
• a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein said first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks,
• a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein said second metal interconnect structure is located at said boundary of the at least two adjacent logic blocks;
• wherein a state of any modifiable cycle is repeatedly programmable by altering any one of the metal layers and/or any one of the vias and
• wherein prior to programming, said first and second metal interconnect structures are coupled at a top metal layer.

In an integrated circuit chip including a plurality of metal layers, first and second supply potentials and at least two adjacent logic blocks, a modifiable circuit for coupling the at least two adjacent logic blocks, comprising:

• a plurality of modifiable cycles coupled together, each cycle having
• a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein said first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks,
• a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein said second metal interconnect structure is located at said boundary of the at least two adjacent logic blocks;
• wherein a state of said any modifiable cycle is repeatedly programmable by altering any one of the metal layers and/or any one of the vias;
• and
• wherein said first and second metal interconnect structures are not electrically coupled to each other at a top metal layer thereby forming two interconnects between the at least two adjacent logic blocks.