U-gate transistors and methods of fabrication

A method of forming a semiconductor transistor structure comprising:

• forming a fin of a semiconductor material on a first insulating layer on a substrate, the fin having a top surface, a first sidewall, and a second sidewall;
• forming a recess in the fin, the recess having a bottom and sidewalls, wherein each of the sidewalls includes at least one step;
• forming a gate dielectric layer on the top surface of the fin, on the first and the second sidewalls of the fin, on the bottom of the recess and on the sidewalls of the recess;
• forming a gate electrode on the dielectric layer;
• and
• forming a drain region and a source region at opposite sides of the gate electrode.

A method of forming a semiconductor structure, comprising:

• forming a fin of a semiconductor material on a first insulating layer, wherein a buffer layer is deposited between a top surface of the fin and a hard mask layer;
• forming a second insulating layer on the fin leaving a top surface of the hard mask layer exposed, wherein a top surface of the second insulating layer is substantially planar with the top surface of the hard mask layer;
• removing the hard mask layer to expose the buffer layer;
• forming spacers on the buffer layer adjacent to the the second insulating layer;
• and
• etching the fin from the exposed portion of the top surface down to the first insulating layer to produce two halved fins.

A method comprising:

• forming a fin of a semiconductor material on a first insulating layer;
• forming a second insulating layer on the fin leaving a top surface of the hard mask layer exposed, wherein a top surface of the second insulating layer is substantially planar with the top surface of the hard mask layer;
• removing the hard mask layer to expose the buffer layer;
• forming spacers on the buffer layer adjacent to a protection layer adjacent to the second insulating layer;
• and
• etching the fin from the exposed portion of the top surface down to a predetermined depth;
• depositing a passivation layer on the bottom of the recess;
• shrinking the spacers in size to expose portions of the top surface of the fin covered by the buffer layer;
• etching away the exposed portions of the top surface of the fin covered by the buffer layer to form the step.