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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Ping Feng, Jung-Chih Tsao, Hsi-Kuei Cheng, Chih-Tsung Lee, Ming-Yuan Cheng, Steven Lin, Ray Chuang, Chi-Wen Liu
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A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
A method of forming a metal interconnect in an opening formed on a substrate, comprising:
A method of forming a copper interconnect in an opening formed in a stack of dielectric layers on a substrate, comprising:
A method of forming a dual damascene structure, comprising:
Dependencies are inferred from the claim text.