Integrated circuit devices having dielectric regions protected with multi-layer insulation structures

A memory device comprising:

• a lower electrode;
• a dielectric layer formed on a predetermined portion of the surface of the lower electrode;
• a spacer layer formed on the lower electrode, the spacer layer comprising a blocking spacer directly contacting a sidewall of the dielectric layer and a protection spacer formed on the blocking spacer;
• an interlayer insulation layer formed on the lower electrode to contact the protection spacer;
• an upper electrode formed on the dielectric layer;
• and
• a multi-layered encapsulating layer surrounding the interlayer insulation layer, the spacer layer and the upper electrode, the multi-layered encapsulating layer comprising a first blocking layer which is annealed and a first protection layer formed on the annealed first blocking layer, the first blocking layer and the first protection layer being formed of the same material.

An integrated circuit, comprising:

• a ferroelectric dielectric region on a substrate;
• a first metal oxide layer directly on a surface of the ferroelectric dielectric region;
• and
• a nonconductive second metal oxide layer on the first metal oxide layer,
• wherein the first metal oxide layer is configured to enable a remnant polarization of the ferroelectric dielectric region to increase during an annealing of the substrate before formation of the second metal oxide layer.