Large-scale trimming for ultra-narrow gates

A method for forming an ultra-narrow gate electrode on a semiconductor wafer comprising:

• patterning a soft mask layer on the semiconductor wafer also having a hard mask layer beneath the soft mask layer, a gate electrode layer beneath the hard mask layer, and a gate dielectric layer beneath the gate electrode layer;
• etching the hard mask layer, resulting in the hard mask layer having a width substantially identical to a width of the soft mask layer as patterned;
• removing the soft mask layer;
• trimming the hard mask layer to further narrow the width of the hard mask layer;
• etching at least the gate electrode layer, such that at least the gate electrode layer has a width substantially identical to the width of the hard mask layer as trimmed, the gate electrode layer as etched being the ultra-narrow gate electrode on the semiconductor wafer;
• and,
• removing the hard mask layer.