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US 6,958,541 B2Granted
Low gate resistance layout procedure for RF transistor devices
AssigneeLSI Logic Corporation
InventorsSean Erickson, Kevin Nunn, Norman Mause
Life of this patent
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Abstract
A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.
Claims13
A transistor structure, comprising:
- a single gate electrode formed of silicided polysilicon,
- a gate signal line, and
- a plurality of conductive plugs formed of a periodic table column IVB, VB, VIB, and/or VIIB metal, each of the plurality of conductive plugs electrically interconnecting the single gate electrode in a distributed manner across a length of the single gate electrode and the gate signal line,
- wherein the single gate electrode, the conductive plug, and the gate signal line are arranged vertically with respect to a substrate upon which the transistor structure is mounted.
1 more element
Dependencies are inferred from the claim text.