Extended length metal line for improved ESD performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShui-Hung Chen, Jian-Hsing Lee, Jiaw-Ren Shih
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Abstract
A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.
Claims14
A multi-level metal interconnect structure for an NMOS transistor containing integrated circuit comprising:
- at least one NMOS transistor disposed along at least one circuit pathway in a multi-level semiconductor device between reference voltage potential and at least one bonding pad comprising one of an input/output signal source and a voltage source;
- and,
- at least one metal interconnect line forming at least a portion of the at least one circuit pathway, the at least one metal interconnect line extended in length along at least a portion of the circuit pathway by forming a compacted serpentine shaped pathway within a predetermined volume of the semiconductor device, the predetermined volume extending through a plurality of metallization levels.
Dependencies are inferred from the claim text.