Non-volatile multi-threshold CMOS latch with leakage control

An integrated circuit (IC) including circuits configured to operate in an active mode and a sleep mode, wherein during the sleep mode the IC maintains a data bit, the IC comprising:

• a first transmission gate comprising an input and an output, the first transmission gate enabled in response to a first control signal;
• a master register (MR) comprises high threshold voltage (HVT) complementary metal oxide semiconductor (CMOS) circuits, a MR input, and a MR output, the MR input electrically connected to the output of the first transmission gate;
• a second transmission gate comprising an input and an output, the second transmission gate electrically connected to the MR output, the second transmission gate enabled in response to a second control signal;
• and
• a slave register (SR) having an input electrically connected to the output of the second transmission gate, the slave register comprising HVT CMOS circuits,
• wherein the first transmission gate comprises LVT CMOS circuits, the second transmission gate comprises HVT CMOS circuits, and during the sleep mode, the first transmission gate is enabled, the second transmission gate is disabled, and the data bit is stored in the slave register.

An electronic device, configured to operate in an active mode and a sleep mode, the electronic device comprising:

• a multiplexer having a plurality of signal inputs and a multiplexer control input, wherein a first signal input is electrically connected to the gates of a first low threshold voltage n-channel circuit and a low threshold voltage p-channel circuit;
• a first transmission gate electrically connected to an output of the multiplexer, the first transmission gate enabled in response to a first control signal;
• a master register comprising high threshold voltage (HVT) complementary metal oxide semiconductor (CMOS) circuits having an input electrically connected to an output of the first transmission gate;
• a second transmission gate electrically connected to an output of the master register, the second transmission gate enabled in response to a second control signal;
• and
• a slave register having an input electrically connected to an output of the second transmission gate, the slave register comprising HVT MOS circuits.

A method of storing a data bit, the method comprising:

• providing a first signal path through a first low threshold voltage (LVT) CMOS circuit;
• providing first high voltage threshold (HVT) circuits in series with the first low threshold CMOS circuit;
• coupling an output from the first signal path to a master register using a first transmission gate;
• latching the data bit in the master register in response to a first phase signal;
• coupling an output of the master register to a slave register using a second transmission gate;
• storing the data bit in the master register in response to a sleep signal, the first transmission gate comprising HVT circuits and the second transmission gate comprising LVT circuits;
• and
• storing the data bit in the slave register in response to a second phase signal, wherein the first and second phase signals are not the same signal.

A method of storing a data bit, the method comprising:

• providing a first signal path through a first low threshold voltage (LVT) CMOS circuit;
• providing a first high voltage threshold (HVT) circuit in series with the first low threshold CMOS circuit;
• coupling an output from the first signal path to a master register using a first transmission gate;
• latching the data bit in the master register in response to a first phase signal;
• coupling an output of the master register to a slave register using a second transmission gate;
• storing the data bit in the slave register in response to a sleep signal, the first transmission gate comprising LVT circuits and the second transmission gate comprising HVT circuits.

An IC comprising:

• means for coupling one of a plurality of input signals to a first switching means, wherein the means for coupling comprises low threshold voltage (LVT) circuits in series with high threshold (HVT) circuits, and wherein the first switching means is enabled in response to a first phase signal;
• a first means for storing a data input signal, the first means for storing electrically connected to an output of the first switching means;
• and
• a second switching means for coupling an output of the first means for storing to an input of a second means for storing, the second switching means being enabled in response to a second phase signal,
• wherein the first switching means comprises LVT circuits and the second switching means comprises LVT circuits.