System and method to improve IC fabrication through selective fusing

A method to facilitate fabricating integrated circuits (ICs) on a wafer having a plurality of die locations comprising:

• measuring at least one respective parameter at a subset of the plurality of die locations on the wafer;
• determining at least one respective parameter for unmeasured die locations on the wafer based at least in part on at least one of the measured parameters associated with at least one of the subset of die locations;
• selectively setting fuses for the plurality of die locations based on at least one of the respective parameters for the respective plurality of die locations to selectively configure ICs at each respective die location;
• computing electrical component parameters for at least some of the plurality of die locations based on at least one of the parameters associated with the respective die locations;
• generating fuse data to control which fuses to set at each of the plurality of die locations based on the computed electrical component parameters;
• selectively setting fuses at each die location based on the fuse data to provide approximately the electrical component parameter computed for each respective die location;
• the respective impedance being computed for each die locations based on the circuit configuration of the ICs so as to provide desired IC performance;
• and
• the ICs at each of the plurality of die locations comprising amplifiers, the respective impedance for each die location further comprising a capacitance, at least some of the parameters for each the respective plurality of die locations indicating an open loop gain and dominant pole locations for the amplifiers, the method further comprising calculating the respective capacitance for each die location to set at least one of the open loop gain and the dominant pole locations for each respective die location.

A method to facilitate fabricating integrated circuits (ICs) on a wafer having a plurality of die locations comprising:

• measuring at least one respective parameter at a subset of the plurality of die locations on the wafer;
• determining at least one respective parameter for unmeasured die locations on the wafer based at least in part on at least one of the measured parameters associated with at least one of the subset of die locations;
• and
• selectively setting fuses for the plurality of die locations based on at least one of respective parameters for the respective plurality of die locations to selectively configure ICs at each respective die location;
• the determining further comprising interpolating to ascertain the at least one respective parameter for the unmeasured die locations;
• calculating respective capacitances for measured and unmeasured die locations based on at least one of the respective parameters associated with the respective measured and unmeasured die locations;
• populating a data table with fuse data to control which fuses to set to achieve the calculated capacitance for ICs at each of the respective die locations;
• and
• selectively setting the fuses based on the fuse data.

A manufacture of integrated circuits (ICs) fabricated on a wafer comprising:

• measuring electrical characteristics associated with at least some of a plurality of die locations on the wafer, die locations at which the electrical characteristics are not measured defining unmeasured die locations;
• computing at least one respective parameter value for at least some of the measured die locations based on at least some of the electrical characteristics measured at the respective die locations;
• determining at least one respective parameter value for at least some of the unmeasured die locations based on the at least one parameter value computed for at least one of the measured die locations;
• and
• selectively setting fuses at each of the plurality of die locations based on at least one of the parameter values for each respective die location to configure ICs at each respective die location.

A method to facilitate manufacture of integrated circuits (ICs) fabricated on a wafer comprising:

• measuring electrical characteristics associated with at least some of a plurality of die locations on the wafer, die locations at which the electrical characteristics are not measured defining unmeasured die locations;
• computing at least one respective parameter value for at least some of the measured die locations based on at least some of the electrical characteristics measured at the respective die locations;
• determining at least one respective parameter value for at least some of the unmeasured die locations based on the at least one parameter value computed for at least one of the measured die locations;
• selectively setting fuses at each of the plurality of die locations based on at least one of the parameter values for each respective die location to configure ICs at each respective die location;
• computing electrical components parameter values for the plurality of die locations based on at least one of the parameter values associated with the respective die locations;
• generating fuse data to control which fuses to set at each of the plurality of die locations based on the computed electrical components parameter values;
• selectively setting fuses for the plurality of die locations based on the fuse data to provide approximately the electrical components parameter values computed for ICs at the respective die locations;
• the electrical component parameter value computed for each die location comprising an impedance;
• and
• the ICs at each of the plurality of die locations comprising an amplifier, the respective impedance computed for each die location further comprising a capacitance, at least one of the parameter values for each respective die location indicating an open loop gain and a dominant pole for the respective amplifier, the method further comprising computing the respective capacitance value for each die location to set at least one of the open loop gain and the dominant pole for the amplifiers at each respective die location.

A system that facilitates fabrication of integrated circuits (ICs) on a wafer having a plurality of die comprising:

• a measurement system that measures at least one electrical parameter at a subset of the plurality of die, the subset of die being spaced apart from each other across the wafer,
• at least one respective parameter associated with unmeasured die being determined based at least in part on the electrical parameter measured for at least one die of the subset of die;
• and
• a fuse system that selectively sets fuses for at least a substantial portion of the plurality of die to configure respective ICs based on the parameter values at the measured and unmeasured die locations.

A system that facilitates fabrication of integrated circuits (ICs) on a wafer having a plurality of die comprising:

• a measurement system that measures at least one parameter at a subset of the plurality of die, the subset of die being spaced apart from each other across the wafer;
• at least one respective parameter associated with unmeasured die being determined based at least in part on the parameter measured for at least one die of the subset of die;
• a fuse system that selectively sets fuses for at least a substantial portion of the plurality of die to configure respective ICs based on the parameter values at the measured and unmeasured die locations;
• and
• the at least one parameter including at least one of a sheet resistance, a head resistance, a capacitance density, a transistor early voltage, a transistor base resistance, a parasitic capacitance, and transistor ft.