Double pattern and etch of poly with hard mask
AssigneeTexas Instruments Incorporated
InventorsTheodore W. Houston, Robert A. Soper, Thomas J. Aton
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Abstract
A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a substrate. A first mask is deposited to pattern the length of the gate by etching, and a second mask pattern is deposited and used to etch the width of the gate, with or without a hard mask.
Claims23
A method of fabricating an integrated circuit, comprising the steps of:
- disposing a layer of material on a substrate;
- forming a first pattern to define opposing sides of an area in the material;
- forming a second pattern, substantially crossing the first pattern, to define an end of the area in the material, where the second pattern is substantially orthogonal to the first pattern at a point where the patterns cross;
- and
- etching the material as defined by the first and second patterns.
A method of fabricating an integrated circuit, comprising the steps of:
- etching an opening in a hard mask with a first pattern;
- adding a sidewall narrowing the opening;
- etching to remove material in the hard mask, with a second pattern, leaving hard mask material on opposite sides of the narrowed opening;
- and
- etching underlying material as masked by the remaining hard mask.
A method of forming a memory array comprising the steps of:
- providing a first pattern, comprising stripes, defining transistor gate length;
- providing a second pattern defining gate ends;
- and
- forming gates within the memory array using the first and second patterns.
A method of fabricating an integrated circuit, comprising the steps of:
- etching an area in a hard mask with a first pattern;
- etching to reduce the width of the area;
- etching to remove additional material in the hard mask with a second pattern;
- etching underlying material as masked by the remaining hard mask.
Dependencies are inferred from the claim text.