US 6,787,426 B2Granted

Method for forming word line of semiconductor device

AssigneeHynix Semiconductor Inc.

InventorWon Chang Lee

Life of this patent

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Abstract

A method for forming word line of semiconductor device wherein a lower portion of the word line on the channel region is a I-type and a upper portion of the word line is a line-type is disclosed. The method comprises (a) forming a sacrificial insulation film on a semiconductor substrate including an active region; (b) etching the sacrificial insulation film to form an I-type sacrificial insulation film pattern whereon a channel region is to be formed; (c) forming a source/drain region; (d) forming a first interlayer insulation film; (e) planarizing the first interlayer insulation film to expose the sacrificial insulation film pattern; (f) sequentially forming a insulation film and a second interlayer insulation film; (g) etching the second interlayer insulation film and insulation film using a word line mask; (h) removing the sacrificial insulation film pattern; (i) growing a gate oxide film; (j) forming a conductive layer; and (k) planarizing the conductive layer.

Claims6

Dependent claims

A method for forming a word line of a semiconductor device, comprising the steps of:

(a) forming a sacrificial insulation film on a semiconductor substrate including a device isolation film defining an active region;
(b) selectively etching the sacrificial insulation film to form an I-type sacrificial insulation film pattern on a predetermined region of the active region where a channel region is to be formed;
(c) forming a source/drain region on the semiconductor substrate at both sides of the sacrificial insulation film pattern;
(d) forming a first interlayer insulation film on the entire surface;
(e) planarizing the first interlayer insulation film to expose a top surface of the sacrificial insulation film pattern;
(f) sequentially forming a insulation film and a second interlayer insulation film on the entire surface;
(g) etching the second interlayer insulation film and insulation film using a word line mask;
(h) removing the sacrificial insulation film pattern to expose the semiconductor substrate;
(i) growing a gate oxide film on the exposed portion of the semiconductor substrate;
(j) forming a conductive layer on the entire surface;
and
(k) planarizing the conductive layer to expose the second interlayer insulation film.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/603,611Filed 26 Jun 2003
Priority: KR 10-2002-4211918 Jul 2002
Published: US 2004/0082155 A129 Apr 2004
Granted: 7 Sep 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10W 20/071
Manufacture or treatment: of dielectric parts thereof
H10D
Inorganic electric semiconductor devices
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by