Random partitionable dot matrix LED display
AssigneeHarvatek Corporation
InventorsBily Wang, Jonnie Chuang
Life of this patent
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Abstract
An array of light emitting diodes (LED) are laid out as a dot matrix array as a display panel. Each LED is accessed by two dimensional addressing from a first set of parallel horizontal interconnections and a second set of orthogonal interconnections. The two sets of orthogonal interconnections are printed on two sides of a substrate. One of the two electrodes of an LED, which mounted on the top of the substrate, is fed through the substrate with a via hole and connected to the orthogonal interconnection at the bottom of the substrate. The size of the display panel is configurable by removing certain rows and/or columns. More than one partitioned blocks can be pieced together by aligning and coupling the corresponding orthogonal interconnections through a motherboard.
Claims9
A random partitionable dot matrix light emitting diode (LED) display panel, comprising:
- an insulating substrate;
- an array of LEDs laid out as a dot matrix on said substrate, each LED having a first electrode and a second electrode;
- a first soldering pad for each said first electrode and a second soldering pad for each said second electrode mounted on said substrate;
- a first set of parallel interconnections printed on the front side of said substrate and each connected to all said first soldering pad for LEDs on a same row;
- and
- a second set of parallel interconnections printed on the backside of said substrate, orthogonal to and insulated from said first set of parallel interconnections, each connected to all said second soldering pad for LEDs on the same column,
- whereby each LED at a cross-point of said first set of parallel interconnections and said second set of parallel interconnections is activated by coincident addressing of one wire from said first set of parallel interconnections and another wire from said second set of parallel interconnections, and
- wherein each said second soldering pad is plated through said substrate and connected to one wire of said second set of parallel interconnections printed in the backside of said substrate.
Dependencies are inferred from the claim text.