Method of forming a via hole in a semiconductor device

A method of manufacturing a semiconductor device comprising the steps of:

• forming a wiring pattern on a primary surface of a semiconductor substrate, the wiring pattern being formed by layering a conductive layer and a layer of material containing nitrogen only on areas of the primary surface comprising the wiring pattern;
• forming an oxide layer to cover the primary surface of the semiconductor substrate and the wiring pattern formed thereon;
• and
• exposing the upper portion surface of the conductive layer at a portion of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and a sidewall of the opening being within a maximum distance of no more than 0.15 μm from an end portion of the wiring pattern.

A method of manufacturing a semiconductor device comprising the steps of:

• (a) forming a wiring pattern on a primary surface of a semiconductor substrate;
• (b) forming an etch resistant layer on the primary surface of the semiconductor substrate;
• (c) forming an electrically insulative layer covering the wiring layer;
• and
• (d) forming a via hole through the insulative layer to the wiring pattern, and if not to the wiring pattern, then to the etch resistant layer;
• wherein the etch resistant layer includes TiN, and
• wherein the via hole is formed having no sidewall more than 0.15 μm from an end portion of the wiring pattern.

A method of manufacturing a semiconductor device comprising the steps of:

• (a) forming a wiring pattern on a primary surface of a semiconductor substrate;
• (b) forming an etch resistant layer on the primary surface of the semiconductor substrate;
• (c) forming an electrically insulative layer covering the wiring layer;
• and
• (d) forming a via hole through the insulative layer to the wiring pattern, and if not to the wiring pattern, then to the etch resistant layer;
• wherein the etch resistant layer is formed only on the wiring pattern, and
• wherein the via hole is formed having no sidewall more than 0.15 μm from an end portion of the wiring pattern.