Semiconductor memory with source/drain regions on walls of grooves

A semiconductor memory device comprising:

• a semiconductor substrate with a groove defined in a surface thereof;
• floating gates supported by the semiconductor substrate, the groove being located so that first and second floating gates are respectively provided on opposite sides of the groove;
• a source/drain region comprising a first impurity layer of a first memory cell and a second impurity layer of a second memory cell that is adjacent to the first memory cell, the first impurity layer having a higher impurity concentration than the second impurity layer;
• and
• wherein the first impurity layer of the first memory cell and the second impurity layer of the second memory cell are formed in opposing sidewalls of the groove, and wherein the first and second impurity layers formed in the opposing sidewalls of the groove are connected to one another via an impurity layer formed in a bottom surface of the groove.

A semiconductor memory device comprising:

• a semiconductor substrate with a groove defined in a surface thereof;
• floating gates supported by the semiconductor substrate, the groove being located so that first and second floating gates are respectively provided at least partially on opposite sides of the groove;
• a source/drain region comprising a first impurity layer of a first memory cell and a second impurity layer of a second memory cell, the first impurity layer having a higher impurity concentration than the second impurity layer;
• and
• wherein the first impurity layer of the first memory cell having the higher impurity concentration and the second impurity layer of the second memory cell are formed in different sidewalls of the groove, and wherein the first impurity layer of the first memory cell and the second impurity layer of the second memory cell share a diffusion layer provided at least in a bottom surface of the groove.