Method for manufacturing memory with high conductivity bitline and shallow trench isolation integration

A method of manufacturing an integrated circuit comprising:

• providing a semiconductor substrate;
• processing the semiconductor substrate to form a core trench and a shallow trench isolation (STI) trench;
• depositing an insulating material in the core trench and the STI trench;
• depositing a photoresist over the core trench and the STI trench;
• processing the photoresist to form a core mask over the STI trench;
• removing the insulating material in the core trench using the core mask;
• removing the core mask;
• depositing a doped bitline material over the core trench and the STI trench;
• planarizing the doped bitline material and the insulating material;
• and
• thermal annealing the doped bitline material to form a high conductivity bitline.

A method of manufacturing a Flash memory integrated circuit comprising:

• providing a semiconductor substrate;
• processing the semiconductor substrate to form a plurality core trenches parallel and spaced apart and a plurality of shallow trench isolation (STI) trenches enclosing portions of the semiconductor substrate;
• depositing an insulating material over and in the core trench and the STI trench;
• depositing a photoresist over the semiconductor substrate, the plurality of core trenches, and the plurality of STI trenches;
• processing the photoresist to form a core mask over a portion of the semiconductor substrate and the plurality of STI trenches;
• removing the insulating material in the plurality of core trenches using the core mask;
• removing the core mask;
• depositing a doped bitline material in the plurality of core trenches and the plurality of STI trenches;
• planarizing the doped bitline material and the insulating material;
• and
• thermal annealing the doped bitline material to form a plurality of high conductivity bitlines.