Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same

A method of forming an SRAM memory cell, comprising:

• forming a plurality of transistors above a semiconducting substrate;
• depositing a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and said transistors;
• depositing a dielectric layer above said BPSG layer, said dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0;
• etching a plurality of openings in said dielectric layer and said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
• and
• forming a conductive local interconnect in each of said openings.

A method of forming an SRAM memory cell, comprising:

• forming a plurality of transistors above a semiconducting substrate;
• forming a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and between said transistors;
• forming a plurality of openings in said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
• forming a conductive local interconnect in each of said openings;
• reducing a thickness of said BPSG, layer after said local interconnects are formed;
• and
• forming a dielectric layer above said BPSG layer and between said conductive local interconnects.

A method of forming an integrated circuit device, comprising:

• forming a plurality of transistors above a semiconducting substrate;
• forming a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and between said transistors;
• forming a plurality of openings in said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
• forming a conductive local interconnect in each of said openings;
• reducing a thickness of said BPSG layer after said local interconnects are formed;
• and
• forming a dielectric layer above said BPSG layer and between said conductive local interconnects.

A method of forming an SRAM memory cell, comprising:

• forming a plurality of transistors above a semiconducting substrate;
• depositing a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and between said transistors;
• etching a plurality of openings in said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
• forming a conductive local interconnect in each of said openings;
• performing at least one etching process to reduce a thickness of said BPSG layer after said conductive local interconnects are formed;
• and
• forming a dielectric layer above said BPSG layer and between said conductive local interconnects, said dielectric layer being comprised of a material having a dielectric constant greater than approximately 6.0.