Single RIE process for MIMcap top and bottom plates
AssigneeInfineon Technologies AG
InventorXian J. Ning
Life of this patent
Estimating the term…
Abstract
A method of forming MIM capacitor top (16) and bottom (12) plates, using a first and second resist (18/20) and a single RIE process. A first conductive layer (12) is deposited over a substrate (10). An insulating layer (14) is deposited over the first conductive layer (12). A second conductive layer (16) is deposited over the insulating layer (14). A first resist (18) is deposited over the second conductive layer (16), and the first resist (18) is patterned. A second resist (20) is deposited over the first resist (18) and patterned. The first and second resist (18/20) patterns are simultaneously transferred to the first and second conductive layers (12) and (16), respectively, by exposure to a single reactive ion etch (RIE) process.
Claims19
A method of patterning metal layers of a semiconductor wafer, the method comprising:
- depositing a first conductive layer over a substrate;
- depositing an insulating layer over the first conductive layer;
- depositing a second conductive layer over the insulating layer;
- depositing a first layer of resist over the second conductive layer;
- patterning the first layer of resist with a first pattern;
- developing said patterned first layer of resist;
- removing portions of said first layer of resist according to said first pattern to expose portions of said second conductive layer;
- depositing a second layer of resist over remaining portions of the first layer of resist and exposed portions of said second conductive layer;
- patterning the second layer of resist with a second pattern;
- developing said patterned second layer of resist;
- stripping portions of said second layer of resist according to said second pattern;
- and
- etching the first conductive layer according to the first pattern and the second conductive layer according to the second pattern in a single etching process.
A method of patterning metal layers of a semiconductor wafer, the wafer comprising a first conductive layer, an insulating layer disposed over the first conductive layer and a second conductive layer disposed over the insulating layer, the method comprising:
- depositing a first layer of resist over the second conductive layer;
- patterning the first layer of resist with a first pattern;
- developing said patterned first layer of resist;
- removing portions of said first layer of resist according to said first pattern to expose portions of said second conductive layer;
- depositing a second layer of resist over remaining portions of the first layer of resist and exposed portions of said second conductive layer;
- patterning the second layer of resist with a second pattern;
- developing said patterned second layer of resist;
- stripping portions of said second layer of resist according to said second pattern;
- and
- etching the first conductive layer according to the first pattern and the second conductive layer according to the second pattern in a single etching process.
A method of forming capacitive plates of a MIM capacitor, comprising:
- providing a wafer having a substrate;
- depositing a first conductive layer on the substrate;
- depositing a capacitor dielectric layer over the first conductive layer;
- depositing a second conductive layer over the capacitor dielectric layer;
- depositing a first layer of resist over the second conductive layer;
- patterning the first layer of resist with a first pattern;
- developing said patterned first layer of resist;
- removing portions of said first layer of resist according to said first pattern to expose portions of said second conductive layer;
- depositing a second layer of resist over remaining portions of the first layer of resist and exposed portions of said second conductive layer;
- patterning the second resist with a second pattern;
- developing said patterned second layer of resist;
- stripping portions of said second layer of resist according to said second pattern;
- and
- etching the first conductive layer according to the first pattern and the second conductive layer according to the second pattern in a single etching process.
Dependencies are inferred from the claim text.