Field programmable gate array based upon transistor gate oxide breakdown
AssigneeKilopass Technologies, Inc.
InventorJack Zezhong Peng
Life of this patent
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Abstract
A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, the capacitor having a dielectric between the first and second terminal. The cell also includes a select transistor having a gate, a source, and a drain, the gate connected to the read bitline, the source connected to the switch control node, and the drain connected to a row wordline. Finally, the cell includes a switch being controlled by the switch control node.
Claims16
A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines, the cell comprising:
- a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, said capacitor having a dielectric between said first terminal and said second terminal;
- a select transistor having a gate, a source, and a drain, said gate connected to said read bitline, said source connected to said switch control node, and said drain connected to a row wordline;
- and
- a switch being controlled by said switch control node.
A method of operating a field programmable gate array (FPGA) comprising a plurality of row wordlines, a plurality of column bitlines, a plurality of read bitlines, and a plurality of FPGA cells at respective crosspoints of the row lines and column bitlines, said cells comprising a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, said capacitor having a dielectric between said first terminal and said second terminal, a select transistor having a gate, a source, and a drain, said gate connected to said read bitline, said source connected to said switch control node, and said drain connected to a row wordline, and a switch being controlled by said switch control node, the method comprising:
- applying a first voltage to a selected one of the column bitlines and gate of a selected one of said select transistor;
- and
- applying a second voltage to a selected one of the row wordlines;
- wherein the first voltage and the second voltage form a potential difference across the dielectric of said capacitor to break down said dielectric converting said capacitor into a resistive device.
A field programmable gate array (FPGA) comprising a plurality of row wordlines, a plurality of column bitlines, a plurality of read bitlines, and a plurality of cells at respective crosspoints of the row wordlines and column bitlines, each of the cells comprising:
- a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, said capacitor having a dielectric between said first terminal and said second terminal;
- a select transistor having a gate, a source, and a drain, said gate connected to said a read bitline, said source connected to said switch control node, and said drain connected to a row wordline;
- and
- a switch being controlled by said switch control node.
Dependencies are inferred from the claim text.