Metal gate electrode stack with a passivating metal nitride layer

Abstract

A low resistance gate stack for an integrated circuit transistor is provided including a metal layer having a first width and a metal nitride over surfaces of the metal layer being less than about 20 Å. The gate stack further includes a doped polysilicon layer underlying the metal layer, the doped polysilicon layer having a second width. In the illustrated embodiment, the metal layer comprises tungsten. In an atmosphere including an oxidant during a source/drain reoxidation process, the gate stack includes at least one surface simultaneously exposed to the oxidant and a passivating species which is adsorbed on the surface of the metal layer. The passivating species inhibits diffusion of the oxidant into the gate stack.

Dependencies are inferred from the claim text.