US 6,607,955 B2Granted

Method of forming self-aligned contacts in a semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorKyu-Hyun Lee

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Abstract

A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to form gate electrode configurations. Sidewall spacers are formed on both sidewalls of the gate electrode configurations. An oxide layer is then deposited on the resulting structure. Selected portions of the oxide layer are etched to form self-aligned contacts that expose the semiconductor substrate. Because the polysilicon has an excellent etch selectivity with respect to the oxide layer, the gate electrode layer can be sufficiently protected during the etching of the oxide layer resulting in a good shoulder margin at the exposed upper edges of the silicon nitride gate mask layer.

Claims26

Dependent claims

A method of forming self-aligned contacts in a semiconductor device, the method comprising:

forming a gate oxide layer, a gate electrode layer, a first gate mask layer, and a second gate mask layer on a semiconductor substrate;
etching the second gate mask layer, the first gate mask layer, and the gate electrode layer to form a plurality of gate electrode configurations which are spaced apart;
forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations;
forming an interlayer insulating layer on an entire surface of the semiconductor substrate;
using a self-aligned contact mask and etching the interlayer insulating layer to expose the semiconductor substrate, removing the self-aligned contact mask;
filling the exposed semiconductor substrate with a conductive material;
and planarizing the conductive material and the second gate mask layer and stopping at the first gate mask,
wherein the first gate mask layer, the second gate mask layer, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer, and
wherein the second gate mask layer has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask layer.

6 more elements

A method of forming self-aligned contacts in a semiconductor device, the method comprising:

forming a plurality of gate electrode configurations which are spaced apart, wherein each gate electrode configuration comprises a gate electrode layer, a first gate mask layer, and a second gate mask layer on a semiconductor substrate;
forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations;
forming an interlayer insulating layer on the gate electrode configurations and the intervening spaces, wherein the first gate mask layer, the second gate mask layer, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer, and wherein the second gate mask layer has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask layer;
using a self-aligned contact mask and etching the interlayer insulating layer to removing the self-aligned contact mask;
filling the exposed semiconductor substrate with a conductive material;
and planarizing the conductive material and the second gate mask layer and stopping at the first gate mask layer, thereby also removing the second gate mask layer during the planarizing of the conductive material, expose the semiconductor substrate.

3 more elements

A method of forming self-aligned contacts in a semiconductor device, the method comprising:

forming a gate oxide layer, a gate electrode layer, a first gate mask layer, a second gate mask layer, and a third gate mask layer on a semiconductor substrate, the third gate mask layer having etching selectivity with respect to the gate electrode layer;
etching the third gate mask layer, the second gate mask layer, and the first gate mask layer;
etching the gate electrode layer, using the third gate mask layer as an etching mask, thus forming a plurality of gate electrode configurations which are spaced apart;
forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations, wherein the third gate mask layer is removed during the forming of the gate spacers;
forming a thin material layer to protect the semiconductor substrate;
forming an interlayer insulating layer on an entire surface of the semiconductor substrate, wherein the first gate mask layer, the second gate mask layer, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer, and wherein the second gate mask layer has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask layer;
and
using a self-aligned contact mask and etching the interlayer insulating layer to expose the semiconductor substrate;
removing the self-aligned contact mask;
filling the exposed semiconductor substrate with a conductive material;
and
planarizing the conductive material and the second gate mask layer and stopping at the first gate mask layer.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/825,346Filed 4 Apr 2001 · continuation in part
Priority: KR 98-2819213 Jul 1998
Published: US 2001/0055867 A127 Dec 2001
Granted: 19 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10P 50/71
Etching of wafers, substrates or parts of devices: using masks for conductive or resistive materials
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered