Method for fabricating semiconductor integrated circuit

A method of fabricating a semiconductor integrated circuit device comprising:

• the step of forming a first electrode over a substrate where a transistor is formed;
• the step of forming a capacitor insulating film over the first electrode;
• the step of forming over the capacitor insulating film a titanium nitride film as a second electrode by a chemical vapor deposition using a source gas containing a halogen element to form a capacitor second electrode;
• the step of forming over the titanium nitride film a first film containing metal atoms bondable to the halogen element and having a greater capability to trap the halogen than tungsten;
• and
• the step of forming an insulating film over the first film,
• wherein the first film is a film deposited by CVD using a material gas with halogen free element or deposited by spattering in halogen free ambient.

A method for fabricating a semiconductor integrated circuit comprising the following steps (a) to (c):

• (a) the step of etching an insulating film formed on the principal plane of a semiconductor substrate to form a contact hole;
• (b) the step of depositing a first conductive film including at least a first TiN film formed by the CVD method using a source gas containing a halogen element over the insulating film including the inside of the contact or via hole and thereafter, removing the first conductive film including the first TiN film over the insulating film and leaving the first conductive film inside the contact or via hole to form a plug inside of the contact or via hole;
• and
• (c) the step of depositing a second conductive film including at least a second TiN film whose lowermost layer is formed by the sputtering method on the insulating film including the surface of the plug and thereafter, patterning a second conductive film including the second TiN film to form wiring.

A method for fabricating a semiconductor integrated circuit having a DRAM obtained by constituting a memory cell with a memory cell selecting MISFET and an information storing capacitive element connected to the memory cell selecting MISFET in series and arranging the information storing capacitive element on the memory cell selecting MISFET, the method comprising:

• (a) the step of forming a memory cell selecting MISFET on the principal plane of a semiconductor substrate to form an MISFET serving as a peripheral circuit in a peripheral circuit region;
• (b) the step of forming a bit line on the memory cell selecting MISFET through a first insulating film and moreover, forming a first-layer wiring on the MISFET serving as a peripheral circuit through the first insulating film;
• (c) the step of forming an information storing capacitive element on the bit line through a second insulating film;
• (d) the step of depositing a third insulating film on the information storing capacitive element and thereafter, etching the third insulating film, the second insulating film, and the first insulating film in the peripheral circuit region to form a contact or via hole on the first-layer wiring;
• (e) the step of depositing a first conductive film including at least a first TiN film formed by the CVD method on the third insulating film including the inside of the contact or via hole and thereafter, removing the first conductive film including the first TiN film on the third insulating film, and leaving only the inside of the contact or via hole to form a plug inside of the contact or via hole;
• and
• (f) the step of depositing a second conductive film including at least a second TiN film whose lowermost layer is formed by the sputtering method on the third insulating film including the surface of the plug and thereafter, patterning the second conductive film including the second TiN film to form a second-layer wiring.