Method of designing/manufacturing semiconductor integrated circuit device using combined exposure pattern and semiconductor integrated circuit device

A method of designing/manufacturing a plurality of semiconductor integrated circuits having built-in ROMs each storing different data on a single wafer, comprising the steps of:

• forming a unique pattern for determining memory data for said built-in ROMs for an uppermost metal layer of a plurality of metal layers;
• combining said unique pattern with a common pattern common to said plurality of semiconductor circuits other than said specific pattern to generate a combined exposure pattern;
• performing, by use of said combined exposure pattern, pattern exposure of a resist film applied to a surface of the wafer in an electron beam exposure apparatus for forming said plurality of semiconductor integrated circuits having said built-in ROMs;
• and
• forming patterns other than said combined unique pattern and said common pattern by using a mask.

A method of forming a plurality of semiconductor integrated circuit devices of chips on a single semiconductor wafer, each of said semiconductor integrated circuit devices having a ROM and an electric circuit cooperative therewith the ROM in the integrated circuit device in each chip storing information unique to the chip and distinct from information stored in the ROM in another semiconductor device on another chip, the method comprising the steps of:

• preparing a common connection conductor pattern which may be used for formation of the electric circuits on the chips in common and a ROM pattern determining information unique to a chip;
• combining said common connection conductor pattern and said ROM pattern into an exposure pattern;
• and
• performing exposure by use of said exposure pattern into which said common connection conductor pattern and said ROM pattern are combined for forming said plurality of semiconductor integrated circuit devices on said chips on said wafer.