Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorSatoyuki Miyako
Life of this patent
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Abstract
The dimension measurement and management of a mask or a wafer are facilitated by using a dummy pattern having a configuration and arrangement capable of achieving a plurality of objects. In the entire region or a major region of an optional wiring layer on a semiconductor chip and in the space between the adjacent patterns in an actual pattern portion, dummy patterns for controlling the coverage and density of a pattern in the wiring layer are regularly arranged. All or some of the dummy patterns are dummy patterns for the dimension measurement including the main size (width and distance) required for the dimension management of the wiring layer.
Claims15
A semiconductor device comprising dummy patterns regularly arranged in the entire region or a major portion of an optional wiring layer on a semiconductor chip, said wiring layer including wiring elements which comprise diffusion layers, polysilicon layers, metal layers and contacts connecting said wiring elements, said dummy patterns controlling the covering rate and density of the pattern in the wiring layer in the space between adjacent patterns of the actual pattern, said dummy patterns including dummy patterns for the dimension measurement of said wiring elements,
- wherein each of said dummy patterns for the dimension measurement is formed of patterns of said wiring elements, including main dimensions required for the dimension management of said wiring layer and each of said dummy patterns for the dimension measurement is arranged regularly.
A semiconductor device comprising dummy patterns for the dimension measurement substituted in a part of the arrangement of a plurality of dummy patterns on a semiconductor chip, said dummy patterns being regularly arranged in the space between the adjacent patterns of an actual pattern portion of an optional wiring layer on a semiconductor chip, said wiring layer including wiring elements which comprise diffusion layers, polysilicon layers, metal layers and contacts connecting the wiring elements;
- wherein said dummy patterns serve to control the covering rate and density of the pattern in the wiring layer on a semiconductor chip, and said dummy patterns for the dimension measurement is formed of patterns of said wiring elements, including the main dimensions required for the dimension management of said wiring layer;
- and
- at least one kind and at least one of said dummy patterns for the dimension measurement is substituted in a part of the arrangement of said dummy patterns.
A semiconductor device, comprising dummy patterns for the dimension measurement substituted in a part of a dummy pattern arrangement on a semiconductor chip, said dummy patterns being regularly arranged in the space between the adjacent patterns of an actual pattern portion of an optional wiring layer on a semiconductor chip, said wiring layer including wiring elements which comprise diffusion layers, polysilicon layers, metal layers and contacts connecting the wiring elements;
- wherein said dummy patterns serve to control the covering rate and density of the pattern in the wiring layer on a semiconductor chip, and said dummy patterns for the dimension measurement is formed of patterns of said wiring elements, including the main dimension required for the dimension management of said wiring layer;
- and
- said dummy pattern for the dimension measurement is arranged in the central portion of a singe rectangular frame-like dummy pattern or in the central portion of a rectangular frame-like arrangement consisting of a plurality of dummy patterns.
Dependencies are inferred from the claim text.