Method for fabricating reduced contacts using retardation layers

An integrated circuit device comprising:

• semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include gate electrodes and associated source/drain regions;
• a first dielectric layer overlying said semiconductor device structures;
• a first patterned conductor layer overlying said first dielectric layer;
• a second dielectric layer having a thickness of between 4000 and 10,000 Angstroms overlying said first patterned conductor layer;
• a retardation layer overlying said second dielectric layer;
• a third dielectric layer overlying said retardation layers and
• a second conducting layer within a contact opening through said first, second, and third dielectric layers and said retardation layer wherein said second conducting layer electrically contacts one of said source/drain regions wherein said contact opening through said third dielectric layer is of a first size and wherein said retardation layer has been etched at an angle and wherein said contact opening through said second and first dielectric layers underlying said angled retardation layer has a second size smaller than said first size completing the fabrication of said integrated circuit device.

An integrated circuit device comprising:

• semiconductor device structures in and on a semiconductor substrate;
• a first dielectric layer overlying said semiconductor device structures;
• a first patterned conductor layer overlying said first dielectric layer;
• a second dielectric layer overlying said first patterned conductor layer;
• a second patterned conductor layer overlying said second dielectric layer;
• a third dielectric layer overlying said second patterned conductor layer;
• a retardation layer overlying said third dielectric layer wherein said retardation layer has a thickness of between about 500 and 2000 Angstroms;
• a fourth dielectric layer overlying said retardation layer wherein said retardation layer has an etch rate slower than an etch rate of said fourth dielectric layer;
• and
• a third conducting layer within a contact opening through said first, second, third, and fourth dielectric layers and said retardation layer wherein said third conducting layer electrically contacts one of said semiconductor device structures wherein said contact opening through said fourth dielectric layer is of a first size and wherein said retardation layer has been etched at an angle and wherein said contact opening through said third, second and first dielectric layers underlying said angled retardation layer has a second size smaller than said first size completing the fabrication of said integrated circuit device.