Integration method for raised contact formation for sub-150 nm devices
AssigneeProMOS Technologies Inc.
InventorBrian Lee
Life of this patent
Estimating the term…
Abstract
An integrated raised contact formation method to achieve ultra shallow junction devices is described. Semiconductor device structures are provided in and on a substrate and covered with a dielectric layer. The dielectric layer is etched through to form first openings to the substrate. The surface of the substrate exposed within the first openings is amorphized. A silicon layer is selectively formed on the amorphized substrate surface. Then, ions are implanted into the silicon layer to form raised contacts. Thereafter, the dielectric layer is etched through to form second openings to gates. The first and second openings are filled with a conducting layer to complete formation of contacts in the fabrication of an integrated circuit device.
Claims30
A method of forming contacts in the fabrication of an integrated circuit device comprising:
- providing semiconductor device structures in and on a substrate;
- covering said semiconductor device structures with a dielectric layer;
- etching through said dielectric layer to form first openings to said substrate;
- amorphizing a surface of said substrate where it is exposed within said first openings;
- selectively forming a polysilicon layer on said amorphized substrate surface wherein said polysilicon layer forms raised contacts;
- implanting ions into said raised contacts;
- thereafter etching through said dielectric layer to form second openings to gates;
- and
- filling said first and second openings with a conducting layer to complete said forming of said contacts in the fabrication of said integrated circuit device.
A method of forming contacts in the fabrication of an integrated circuit device comprising:
- providing semiconductor device structures in and on a substrate;
- covering said semiconductor device structures with a dielectric layer;
- etching through said dielectric layer to form first openings to said substrate;
- amorphizing a surface of said substrate where it is exposed within said first openings;
- selectively forming a polysilicon layer on said amorphized substrate surface using a hemispherical grain process to form raised contacts;
- implanting ions into said raised contacts;
- thereafter etching through said dielectric layer to form second openings to gates;
- and
- filling said first and second openings with a conducting layer to complete said forming of said contacts in the fabrication of said integrated circuit device.
A method of forming contacts in the fabrication of an integrated circuit device comprising:
- providing semiconductor device structures in and on a substrate;
- covering said semiconductor device structures with a dielectric layer;
- etching through said dielectric layer to form first openings to said substrate;
- amorphizing a surface of said substrate where it is exposed within said first openings;
- selectively forming a polysilicon layer on said amorphized substrate surface using a hemispherical grain process to form raised contacts;
- implanting ions into said raised contacts wherein said implanting comprises an energy of less than 30 KeV and a dosage of more than 3E15 ions/cm2;
- thereafter etching through said dielectric layer to form second openings to gates;
- and
- filling said first and second openings with a conducting layer to complete said forming of said contacts in the fabrication of said integrated circuit device.
Dependencies are inferred from the claim text.