US 6,441,429 B1 · Split-gate flash memory device having floating gate electrode with sharp peak

Abstract

A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as an option. On the top surface of the first polysilicon layer, a silicon nitride layer was etched to form it into a cell-defining layer. A polysilicon oxide dielectric cap was formed over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, the first polysilicon layer and the tunnel oxide layer were formed into a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Spacers are formed on the sidewalls of the gate electrode stack. Blanket inter-polysilicon dielectric and blanket control gate layers cover exposed portions of the substrate and the stack. The inter-polysilicon dielectric and control gate layers are patterned into a split gate electrode pair. A source region is self-aligned with the floating gate electrode stack. A tungsten silicide anneal was performed; and a drain region self-aligned with the control gate electrodes was formed.

Claims10

Dependent claims

A split gate electrode MOS FET device comprising:

a tunnel oxide layer having an top surface, the tunnel oxide layer being formed over a semiconductor substrate,
a first doped polysilicon layer having an upper surface, the first doped polysilicon layer being formed on the top surface of the tunnel oxide layer,
a cap formed on the upper surface of the first doped polysilicon layer,
a floating gate electrode stack formed from the tunnel oxide layer and the first doped polysilicon layer in the pattern of the cap with said first doped polysilicon layer comprising a floating gate electrode with a cross-sectional bird's beak having a peak along the periphery thereof adjacent to the cap,
a source region and a drain region self-aligned with the gate electrode stack,
an inter-polysilicon dielectric layer and a control gate layer formed over exposed portions of the substrate covering the stack, and
the inter-polysilicon dielectric and control gate layers being patterned into a split gate electrode pair.

4 more elements

A split gate electrode MOS FET device comprising:

a tunnel oxide layer over a semiconductor substrate, the tunnel oxide layer having a top surface,
a floating gate electrode layer formed on the top surface of the tunnel oxide layer, the floating gate electrode layer having an upper surface,
a cap formed on the upper surface of the floating gate electrode layer,
a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the cap,
a floating gate electrode stack formed from the tunnel oxide layer and the floating gate electrode in the pattern of the cap with the floating gate electrode layer comprising a the floating gate electrode with a cross-sectional bird's beak having a sharp peak along the periphery thereof adjacent to the cap,
inter-polysilicon dielectric and control gate layers over the substrate covering the stack,
the inter-polysilicon dielectric and control gate layers comprising adjacent mirror image split gate electrode pairs, and
a source region self-aligned with the floating gate electrode stack,
a drain regions self-aligned with the control gate electrode.

6 more elements

Dependencies are inferred from the claim text.

Split-gate flash memory device having floating gate electrode with sharp peak

Life of this patent

Split-gate flash memory device having floating gate electrode with sharp peak

Life of this patent

Abstract

Claims10