Method to reduce polysilicon depletion in MOS transistors

A method of reducing polysilicon depletion in polysilicon electrodes in MOS transistors comprising the steps of:

• providing a substrate;
• forming a pad oxide layer over said substrate;
• forming a nitride layer over said pad oxide layer;
• patterning said nitride layer to form a trench over said pad oxide layer;
• removing said pad oxide layer and exposing said substrate at the bottom of said trench;
• optionally forming and removing a sacrificial layer;
• forming a gate oxide layer over said substrate at the bottom of said trench;
• forming a polysilicon layer over said substrate, including within said trench;
• performing chemical mechanical polishing (CMP) to remove excess polysilicon over said trench;
• selective etching said polysilicon layer in said trench to a desired thickness;
• in-situ amorphizing upper portion of said polysilicon layer by implanting ions into said polysilicon layer to form an amorphous (α-Si) layer over said polysilicon layer;
• doping said polysilicon layer by implanting ions;
• performing laser irradiation of selected wavelength and fluence to melt and regrow said α-Si layer while at the same time driving said ions deeply into said polysilicon electrode reaching but adjacent said underlying oxide layer;
• and
• continuing the completion of said MOS transistor by a depositing another material into said trench followed by CMP to form a contact.