Method for fabricating semiconductor device having a HSG layer

Abstract

In a method for fabricating a semiconductor device including a stacked structure memory cell having a transistor and a capacitor stacked over the transistor, a lower electrode of opposing electrodes of the capacitor is formed by forming a high-concentration impurity-doped amorphous silicon layer on an interlayer insulator film and patterning the amorphous silicon layer into an electrode shape, generating crystal nuclei on a surface of the patterned amorphous silicon layer and growing the crystal nuclei to form crystalline grains of silicon on an upper surface and a side surface of the patterned amorphous silicon layer, and forming a high-concentration impurity-doped polysilicon film on the crystalline grains and the amorphous silicon layer. Thus, the impurity concentration at the surface of the crystalline grains is compensated for. As a result, a stacked capacitor having less bias voltage dependency of the capacitance can be obtained.

Claims aren’t available for this document.