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US 6,310,361 B1Granted
Electrical test structure on a semiconductor substrate and test method
AssigneeInfineon Technologies AG
InventorGerd Lichter
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Abstract
The test structure has a row of transistors with at least two transistors. The S/D regions of the transistors are connected in series and the first and the last S/D region in the row can be connected. Possible etching of the gate polysilicon can be ascertained by measuring the resistance between the terminals given a suitable gate potential. The invention enables, in particular, in situ monitoring of a KOH attack on the n-doped gate polysilicon in a DRAM memory cell.
Claims11
A semiconductor test structure for in situ determination of an etching attack on polysilicon, comprising:
- a semiconductor substrate;
- a plurality of MOS transistors formed in said semiconductor substrate;
- each of said transistors having a gate with a doped polysilicon layer for evaluating said etching attack and a conductive layer disposed above said polysilicon layer, a first S/D region and a second S/D region, said gate having a covering insulation layer and insulating sidewall spacers;
- said gates of said transistors being electrically connected to one another and having a terminal;
- said second S/D region of a first one of said transistors being electrically connected to said first S/D region of a second one of said transistors;
- and
- said first S/D region of said first transistor being connected to a first terminal and said second S/D region of the second transistor is connected to a second terminal.
4 more elements
Dependencies are inferred from the claim text.