Process for semiconductor device fabrication having copper interconnects

Abstract

A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. At least one recess is formed in the layer of dielectric material. Barrier layers and seed layers for electroplating are then deposited over the entire surface of the substrate. The recess is then filled with copper by electroplating copper over the surface of the substrate. The electroplated copper has an average grain size of about 0.1 μm to about 0.2 μm immediately after deposition. The substrate is then annealed to increase the grain size of the copper and to provide a grain structure that is stable over time at ambient conditions and during subsequent processing. After annealing, the average grain size of the copper is at least about 1 μm in at least one dimension. The copper that is electroplated on the dielectric layer is then removed using an expedient such as chemical mechanical polishing. The copper that remains is the copper in the recess.

Dependencies are inferred from the claim text.