Method for forming a semiconductor memory device with increased coupling ratio
AssigneeHyundai Electronics Industries Co., Ltd.
InventorHee-Cheol Jeong
Life of this patent
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Abstract
A semiconductor memory device and a method for manufacturing a semiconductor memory device for increasing the coupling ratio are disclosed. In the memory device, a tunneling insulating film is formed on a semiconductor substrate. A floating gate is formed on the tunneling insulating film. A dielectric layer is formed on the surface of the floating gate. A control gate having a predetermined shape is formed on the dielectric layer. The capacitance between the control gate and the floating gate is increased, enlarging the coupling ratio. As a result, the power consumption can be reduced and the access time can be decreased.
Claims16
A method for manufacturing a semiconductor memory device, comprising the steps of:
- forming a tunneling film and a first conductor layer on a semiconductor substrate;
- forming a second conductor layer connected to the first conductor layer so as to form a floating gate;
- forming a dielectric layer on the floating gate;
- forming a control gate on the dielectric layer;
- and
- forming first and second impurity regions in the semiconductor substrate adjacent the floating gate, such that the first and second conductor layers are connected together overlying a portion of the semiconductor substrate between the first and second impurity regions.
A method for manufacturing a semiconductor memory device, comprising the steps of:
- forming a tunneling film and a first conductor layer on a semiconductor substrate;
- forming a second conductor layer having a contact hole therethrough on the first conductor layer so as to form a floating gate;
- forming a dielectric layer on a surface of the floating gate;
- forming a control gate on the dielectric layer;
- and
- forming first and second impurity regions in the semiconductor substrate adjacent the floating gate, such that the contact hole is overlying a portion of the semiconductor substrate between the first and second impurity regions.
A method for manufacturing a semiconductor memory device comprising:
- forming a tunnel oxide on a substrate;
- forming a floating gate above the tunnel oxide, the floating gate having at least one protrusion;
- forming a dielectric layer to cover surfaces of the floating gate;
- forming a control gate on the dielectric layer, the control gate having at least one protrusion;
- and
- forming impurity regions in the substrate, the impurity regions being electrically connected with the floating gate,
- wherein the control gate surrounds the protrusion of the floating gate.
A method for manufacturing a semiconductor memory device comprising:
- forming a tunnel oxide on a substrate;
- forming a floating gate above the tunnel oxide, the floating gate having at least one protrusion;
- forming a dielectric layer to cover surfaces of the floating gate;
- forming a control gate on the dielectric layer, the control gate having at least one protrusion;
- and
- forming impurity regions in the substrate, the impurity regions being electrically connected with the floating gate,
- wherein the floating gate surrounds the protrusion of the control gate.
Dependencies are inferred from the claim text.