Semiconductor device with salicide structure and fabrication method thereof
AssigneeNEC Corporation
InventorsYoshihisa Matsubara, Masato Kawata
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AssigneeNEC Corporation
InventorsYoshihisa Matsubara, Masato Kawata
Estimating the term…
A semiconductor device is provided, which makes it possible to decrease the electric sheet resistance of source/drain regions of MOSFETs in a peripheral circuitry without degradation of the data writing speed in nonvolatile memory cells. This device is comprised of nonvolatile memory cells and a peripheral circuitry provided on a same semiconductor substrate. The nonvolatile memory cells are formed by a first plurality of MOSFETs of a first conductivity type. The peripheral circuitry includes a second plurality of MOSFETs of the first conductivity type. Each of the first plurality of MOSFETs is equipped with a gate electrode having a floating age for data storing and source/drain regions having substantially no silicide films. Each of the second plurality of MOSFETs is equipped with source/drain regions having silicide films and a doping concentration lower than that of the source/drain regions of each of the first plurality of MOSFETs. It is preferred that the doping concentration of the source/drain regions of the first plurality of MOSFETs is equal to 1×1019 atoms/cm3 or higher and the doping concentration of the source/drain regions of the second plurality of MOSFETs is lower than 1×1019 atoms/cm3.
A fabrication method of a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.