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US 6,294,812 B1Granted
High density flash memory cell
AssigneeUnited Microelectronics Corp.
InventorsYen-Lin Ding, Gary Hong
Life of this patent
Estimating the term…
Abstract
A flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.
Claims22
A flash memory cell, comprising:
- a substrate;
- a shallow trench isolation;
- a drain region and a source region adjacent to the shallow trench isolation in the substrate;
- a channel region between the drain region and the source region in the substrate;
- a gate oxide layer over the channel region;
- a tunneling layer covering the source region and the drain region;
- a floating gate, on the gate oxide layer and the tunneling layer;
- a dielectric layer, on the floating gate;
- and
- a controlling gate, on the dielectric layer.
7 more elements
A flash memory cell, comprising:
- a substrate;
- a plurality pairs of doped regions in the substrate, each pair of the doped region being isolated by a shallow trench isolation;
- a channel region, between two doped regions of each pair in the substrate;
- a gate oxide layer, on the channel region on the substrate;
- a tunneling layer, covering each pair of the doped region;
- a first polysilicon layer, covering the tunneling layer and the gate oxide layer;
- a dielectric layer, covering the first polysilicon layer;
- and
- a second polysilicon layer, covering the dielectric layer.
6 more elements
Dependencies are inferred from the claim text.