US 6,294,810 B1Granted

EEPROM cell with tunneling at separate edge and channel regions

AssigneeVantis Corporation

InventorsXiao-Yu Li, Steven J. Fong

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Abstract

An EEPROM cell is described that is programmed and erased by electron tunneling at separate regions, an edge of a tunneling drain and a sense transistor channel. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer by electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer be electron tunneling at an edge of a tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain.

Claims19

Dependent claims

An EEPROM cell, comprising:

a semiconductor substrate, said semiconductor substrate having a first conductivity type;
a tunneling transistor formed in said semiconductor substrate, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having a second conductivity type that is opposite said first conductivity type;
a tunnel oxide layer overlying said tunneling channel, said tunneling source and said tunneling drain;
a program junction region formed in said semiconductor substrate, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said second conductivity type;
a program junction oxide layer overlying said program junction region;
a sense transistor formed in said semiconductor substrate and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said second conductivity type;
a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;
a read transistor formed in said semiconductor substrate, said read transistor having a read source and a read drain, said read transistor electrically coupled to said sense transistor through said sense drain;
and
a floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer, wherein electron tunneling through said tunnel oxide layer overlying an edge of said tunneling drain occurs upon incurrence of a sufficient voltage potential between said floating gate and said tunneling drain, and wherein electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said sense channel.

7 more elements

An EEPROM cell, comprising:

a semiconductor substrate, said semiconductor substrate having a P conductivity type;
a tunneling transistor formed in said semiconductor substrate, said tunneling transistor having a tunneling source, a tunneling drain and a tunneling channel between said tunneling source and said tunneling drain, said tunneling drain and said tunneling source having an N conductivity type, said tunneling drain being electrically coupled to a word bit line;
a program junction region formed in said semiconductor substrate, said program junction region separated from said tunneling transistor by a first oxide, said program junction region having said N conductivity type, said program junction region being electrically coupled to an array control gate;
a program junction oxide layer overlying said program junction region;
a sense transistor formed in said semiconductor substrate and separated from said program junction region by a second oxide, said sense transistor having a sense source, a sense drain and a sense channel between said sense source and said sense drain, said sense source and said sense drain having said N conductivity type, said sense source being electrically coupled to a product term ground;
a sense tunnel oxide layer overlying said sense channel, said sense source and said sense drain;
a read transistor formed in said semiconductor substrate, said read transistor electrically coupled to said sense transistor through said sense drain, said read transistor having a read source and a read drain, said read source and said read drain having said N conductivity type, said read drain being electrically coupled to a product term;
a read gate oxide layer overlying said read channel;
and
a floating gate overlying said tunnel oxide layer, said program junction oxide layer and said sense tunnel oxide layer, wherein electron tunneling through said tunnel oxide layer overlying an edge of said tunneling drain occurs upon incurrence of a sufficient voltage potential between said floating gate and said tunneling drain, and wherein electron tunneling through said sense tunnel oxide layer overlying said sense channel occurs upon incurrence of a sufficient voltage potential between said floating gate and said sense channel.

7 more elements

Dependencies are inferred from the claim text.